In the prior art, three sub-pixel regions for display in red (R), green (G) and blue (B) are arranged from left to right in a primary pixel region of a display panel, each primary pixel region has a square or circular shape, each sub-pixel region has a rectangular shape that is defined by short sides and long sides. The short sides of each sub-pixel region are parallel to the gate lines, as shown in FIG. 1. The conventional display having a resolution of m×n includes m gate lines GATE1, GATE2, GATE3, . . . GATEm−2, GATEm−1 and GATEm and 3n data lines D1, D2, D3, . . . D3n−3, D3n−2, D3n−1 and D3n. Generally, such arrangement mode of sub-pixel regions is referred to as a vertical arrangement mode.
Depending on the driving modes, the pixel structure of a flat panel display may be a single-gate-driven pixel arrangement mode, a dual-gate-driven pixel arrangement mode and a tri-gate-driven pixel arrangement mode. In the single-gate-driven pixel arrangement mode, the three-color sub-pixel regions are driven together by a single gate driver; in the dual-gate-driven pixel arrangement mode, the three-color sub-pixel regions are driven together by two gate drivers; and in the tri-gate-driven pixel arrangement mode, the three-color sub-pixel regions are driven by three gate drivers.
Generally, in a 3D display, the right and left eyes of a person see different images, the raster grids provided in front of the display panel need to be arranged vertically, with the size of a raster grid being close to the size of a primary pixel region. Because of a positioning error between the glass plate on which the raster grids are provided and the display panel during assembly, the raster grids may block a certain colour, for example, a part of the area of the red sub-pixel region may be covered, thus causing a serious colour offset and chromatic aberration. In order to solve this problem, a lateral arrangement mode is proposed in the prior art, that is, various colour sub-pixel regions are arranged laterally. Thus, even if a positioning error occurs between the glass plate on which the raster grids are provided and the display panel during assembly, the same area of each of the three colour sub-pixel regions will be blocked; as a result, although the light transmitted by each sub-pixel region is decreased, the colour formed by the three sub-pixel regions is not offset. Currently, the lateral pixel arrangement mode may be one of a single-gate-driven lateral pixel arrangement mode in which a vertical screen is laterally utilized, a dual-gate-driven lateral pixel arrangement mode, or a tri-gate-driven lateral pixel arrangement mode.
The principle of the single-gate-driven lateral pixel arrangement mode in which a vertical screen is laterally-utilized is to rotate a screen with a resolution of m×n into a screen with a resolution of n×m. In such an arrangement mode, a buffer needs to be added to the driving circuit for the lateral-to-vertical conversion of a display signal, but this will greatly increase the system costs. Therefore, such an arrangement mode is rarely applied.
Comparing the single-gate-driven lateral pixel arrangement mode in which a vertical screen is laterally utilized to the tri-gate-driven lateral pixel arrangement mode, the number of the gate lines is three times of that of the single-gate-driven lateral pixel arrangement mode in which a vertical screen is laterally utilized, but the number of the data lines thereof is one-third of that of the single-gate-driven lateral pixel arrangement mode in which a vertical screen is laterally utilized, thus a display panel employing the tri-gate-driven lateral pixel arrangement mode uses more gate driving chips, but less source driving chips. Because the number of the gate lines is three times that of single-gate-driven lateral pixel arrangement mode in which a vertical screen is laterally utilized, and the driving time of each gate line is shortened to one-third of that of single-gate-driven lateral pixel arrangement mode in which a vertical screen is laterally utilized; in the case of a high resolution display, it is difficult for the manufacturing process of conventional thin film transistors (TFTs) to meet the driving requirements.